A major goal in the design and manufacture of electronic circuitry is to increase the accuracy, precision and capability of wireless handheld devices such as cellular phones. The newer types of cellular phones incorporate digital cameras and data service features. These features require the presence of high density, high color display modules. This means that there is an increasing need for wide, high-speed parallel interfaces to interconnect between baseband processors, application processors, image processors and the input/output (I/O) devices that they support (such as digital cameras and display modules).
One type of interface used in such devices is referred to as a Mobile Pixel Link (MPL). The MPL interface uses a very low power, low electromagnetic interference (EMI) current mode transceiver technology. The MPL interface is capable of supporting digital camera interfaces, color RGB (red, green, blue) interfaces, and central processing unit (CPU) interfaces.
A block diagram of an exemplary prior art high common mode input mobile pixel link (MPL) receiver 100 is illustrated in FIG. 1. A transmitter represented by current source IDC provides a data signal through transmission line 110 to current conveyor 120 of receiver 100. The output of transmission line 110 is coupled to a first end of matching resistor R. In one commonly encountered embodiment transmission line 110 has an impedance of fifty ohms (50Ω) and matching resistor R has a resistance of fifty ohms (50Ω).
The second end of matching resistor R is coupled to a node in current conveyor 120 that is designated “acgnd” (representing an “alternating current (AC) ground”). Current conveyor 120 comprises two NMOS (N-type metal oxide semiconductor) transistor circuits. The first transistor (NMOS transistor M1) is designated “MNIN” and the second transistor (NMOS transistor M2) is designated “MN Bias”.
As shown in FIG. 1, the source of the first transistor MNIN and the gate of the second transistor MN Bias are both coupled to the “acgnd” node. The source of the second transistor MN Bias is coupled to ground. The gate of the first transistor MNIN and the drain of the second transistor MN Bias are both coupled to a node in current conveyor 120 that is designated “ning”.
The drain of the first transistor MNIN is coupled to current source IDC through a node that is designated “Low Swing”. The gate of the first transistor MNIN and the drain of the second transistor MN Bias are both coupled to current source ILOW through the “ning” node. The “Low Swing” node is coupled to the input of a clamp circuit 130 that comprises an NMOS (N-type metal oxide semiconductor) transistor designated “MNFB” and a PMOS (P-type metal oxide semiconductor) transistor designated “MPFB”. The “Low Swing” node is also coupled to an input of inverter circuit 140. The output of the clamp circuit 130 and the output of inverter circuit 140 are coupled to a node that is designated “High Swing”. The “High Swing” node is coupled to an input of inverter circuit 150. The output of inverter circuit 150 is provided to an output terminal designated “OUT”.
The low common mode voltage of prior art MPL receiver 100 can create problems for a transmitter in the presence of noise. Cellular noise affects both the MPL Level Zero current level (450 microamperes) and the MPL Level One current level (2 milliamperes). To reduce the cellular noise effects it would be desirable to raise the input common mode voltage as high as possible. However, raising the input common mode voltage must be done without adversely affecting the functionality of the MPL receiver 100.
Because the MPL transceiver is the first circuitry to fail, raising the input common mode voltage of the MPL receiver 100 will give more headroom on the MPL transmission line. However, when the voltage is increased at the “acgnd” node in current conveyor 120, two failures will occur in the following order.
First, note that the “Low Swing” node in MPL receiver 100 is a fixed voltage when the data current is modeled by a static current. Typically the fixed voltage on the “Low Swing” node is one half of the supply voltage (i.e., nine tenths of a volt (0.9 V)). If the voltage at the “acgnd” node is increased, then the drain to source voltage (VDS) of the first transistor MNIN will be decreased. This will cause the first transistor MMIN to go into the triode state and will distort the response of the current conveyor 120. (This is Problem No. 1).
Second, assume that the voltage at the “acgnd” node can be increased without creating Problem No. 1. Increasing the voltage at the “acgnd” node will cause the voltage at the “ning” node to increase. This will eventually cause the current that flows through the second transistor MN Bias to decrease. This will cause a loss of gain in current conveyor 120. (This is Problem No. 2).
Assume that the voltage at the “acgnd” node can be increased without creating Problem No. 1 and without creating Problem No. 2. In that case, increasing the voltage at the “acgnd” node would create either (1) a loss of gain, or (2) an increase in current consumption. (This is Problem No. 3).
There is therefore a need in the art for a system and method for providing an improved current conveyor circuit in a mobile pixel link (MPL) receiver. In particular, there is a need in the art for an improved current conveyor circuit in a mobile pixel link (MPL) receiver that can provide an increased input common mode voltage to allow a greater tolerance of noise on an MPL transmission line.